Title:
【発明の名称】回路基板検査方法
Document Type and Number:
Japanese Patent JP3020067
Kind Code:
B2
Abstract:
PURPOSE:To omit meaningless inspection over each board by inspecting the respective printed circuit boards in a mother board to be inspected according to the combination of the measuring step order and pin number stored in a main body memory. CONSTITUTION:A plurality of board fixtures 1, 2, 3 are provided and, for example, three printed circuit boards S4 - S6 different in circuit constitution are set to the respective fixtures 1, 2, 3 and, when an one pin-to-other all remaining pins test is carried out, the probe pins of the circuit boards S4 - S6 are brought to a contact state and the one pin-to-other all remaining pins test is carried out with respect to said boards. At the time of the inspection of the boards, inspection data are successively read from the respective memory regions of a main body memory to carry out the one pin-to-other all remaining pins test with respect to the circuit boards S4 - S6. In this case, by adding offset values, the probe pin belonging to each fixture is discriminated from the probe pins belonging to the other fixtures and, therefore, the one pin-to-other all remaining pins test is not carried out over the circuit boards S4 - S6.
Inventors:
Shinichi Seki
Hideaki Wakamatsu
Kazuhiro Mori
Koichi Yamamoto
Yoshifumi Yoshizawa
Hideaki Wakamatsu
Kazuhiro Mori
Koichi Yamamoto
Yoshifumi Yoshizawa
Application Number:
JP14576090A
Publication Date:
March 15, 2000
Filing Date:
June 04, 1990
Export Citation:
Assignee:
Hioki Electric Co., Ltd.
International Classes:
G01R27/02; G01R31/28; H05K3/00; G01R31/02; (IPC1-7): G01R31/28; G01R27/02; G01R31/02
Attorney, Agent or Firm:
Takuya Ohhara