PURPOSE: To improve and make fast a CS timing by outputting a CS signal outputted from a CS input buffer to a CS buffer with each different timing of a reading action and a writing action.

CONSTITUTION: An NOR circuit 1 is provided at an input first step, and after a second step, the signal channel is divided into a channel for reading and that for writing. At the channel for reading, an inverter circuit 2a having the larger channel width of an NCh transistor than a usual ratio type inverter is provided at the second step, and the usual ratio type inverter 3a is provided at a third step. At a channel for writing, usual ratio type inverter circuits 2b and 3b are provided at the second step and the third step. Thus, at the time of reading and the time of writing, a CS signal is optimized, and thus, the reading action can be made fast and the CS access can be made high-speedy.