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Patent Searching and Data


Title:
FAULT PROCESSING VERIFYING SYSTEM
Document Type and Number:
Japanese Patent JPH0675807
Kind Code:
A
Abstract:

PURPOSE: To execute an inspection in a short time, and also, at a low cost by collating actual fault information subjected to logging and fault information of a generated expected value and verifying a fault processing.

CONSTITUTION: A detaching means 3 detaches a device group for constituting the system into one set of specific processing device 1 and the remaining other device 2. In this case, by an artificial fault generating means 4, a specific artificial fault 41 is generated by the other device 2, and when the specific artificial fault 41 is generated in the other device 2, an expected value generating means 5 generates an expected value of fault information to be subjected to logging by an operating system 21. Accordingly, when the specific artificial fault 41 is generated by the artificial fault generating means 4, a collating means 6 collates the fault information subjected to logging by the operating system 21 and the expected value generated by the expected value generating means 5, therefore, based on a result of collation by the collating means 6, a fault processing can be verified.


Inventors:
TAKAHASHI YUMI
MIYAHARA SHINJI
Application Number:
JP22766192A
Publication Date:
March 18, 1994
Filing Date:
August 27, 1992
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/22; (IPC1-7): G06F11/22; G06F11/22
Attorney, Agent or Firm:
Teiichi