Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH0541494
Kind Code:
A
Abstract:
PURPOSE: To provide a semiconductor integrated circuit which can reduce the dispersed extent of the resistance set value of a pull-up or pull-down resistance.
CONSTITUTION: A pull-up resistance is formed by connecting a P-channel MOS transistor, the source, gate, and drain of which are respectively connected to a power supply terminal 52, prescribed control terminal 51, and prescribed circuit connecting terminal 53, and another P-channel MOS transistor 2, the source, gate, and drain of which are respectively connected to the terminal 52, a grounding point, and terminal, 53, in parallel with each other.
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Inventors:
AZUMA YOJI
Application Number:
JP19757391A
Publication Date:
February 19, 1993
Filing Date:
August 07, 1991
Export Citation:
Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
H01L21/8238; H01L27/092; (IPC1-7): H01L27/092
Attorney, Agent or Firm:
Uchihara Shin
Next Patent: APPARATUS FOR MACHINING BY ELECTRICITY