Title:
【発明の名称】半導体記憶装置の製造方法
Document Type and Number:
Japanese Patent JP3059668
Kind Code:
B2
Abstract:
PURPOSE: To improve the information erasing efficiency and information writing characteristic by constituting a field effect transistor for flash type nonvolatile memory element in a manner that its source area is heavily doped and has a large joint depth and a drain area is lightly doped and has a small joint depth. CONSTITUTION: The heavily doped n<+> type semiconductor area 11 in a source area is constituted mainly as to increase the impurity concentration and make the joint depth large. The lightly doped n type semiconductor area 12 is constituted mainly as to make the joint depth large. In addition, the lightly doped n type semiconductor area 14 in a drain area is constituted as to be lightly doped and has a small joint depth in comparison with the heavily doped area 11 in the source area, however its concentration is set appropriately for producing hot electrons during writing operation.
Inventors:
Kazuhiro Komori
Toshiaki Nishimoto
Rei Meguro
Hitoshi Kume
Yoshiaki Kamigaki
Toshiaki Nishimoto
Rei Meguro
Hitoshi Kume
Yoshiaki Kamigaki
Application Number:
JP28949995A
Publication Date:
July 04, 2000
Filing Date:
November 08, 1995
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP2372A | ||||
| JP2129968A | ||||
| JP2128477A | ||||
| JP62276878A | ||||
| JP6271277A | ||||
| JP61127179A | ||||
| JP61123186A | ||||
| JP60207385A |
Attorney, Agent or Firm:
Shuuki Akita