Title:
【発明の名称】真空マイクロエレクトロニクスによるトランジスタの製造方法
Document Type and Number:
Japanese Patent JP3042011
Kind Code:
B2
Abstract:
PURPOSE:To shorten distances among electrodes of a transistor by etching in the plural direction slantwise with respect to a main surface by the use of masks formed on a stepped electrode surface layer. CONSTITUTION:A tungsten layer 1 formed on a base made of silicon oxide is machined. Portions divided by slantwise etching serve as an emitter electrode 2, a pair of base electrodes 3 and a collector electrode 4. The surface portion 3a of the electrode 3 is lower than the surface portion 2a of the electrode 2 and higher than the surface portion 4a of the electrode 4, that is, there are steps in the electrodes 2, 3, 4. If a mask is formed on the surface of an electrode material layer having the steps and in a plane parallel to the main surface thereof, the mask has openings at remarkably small intervals at the steps. With application of slantwise etching in the plural directions by the use of the mask, distances among the electrodes 2, 3, 4 can become short owing to the steps. Consequently, heat can be radiated with high efficiency, thus achieving operation at a high speed.
Inventors:
Ryuichi Ugajin
Application Number:
JP11543191A
Publication Date:
May 15, 2000
Filing Date:
April 19, 1991
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H01J9/02; H01J19/24; H01J21/06; H01J21/10; H01L21/331; H01L29/73; (IPC1-7): H01J9/02; H01J19/24; H01J21/10
Domestic Patent References:
| JP340332A | ||||
| JP4253139A |
Attorney, Agent or Firm:
Akira Koike (3 others)