Title:
【発明の名称】プログラマブル論理回路装置
Document Type and Number:
Japanese Patent JP2548301
Kind Code:
B2
Abstract:
A programmable logic device includes: a programmable AND array (14); an OR array (17) operatively connected to the AND array; a plurality of external terminals (I/O1 SIMILAR I/On); and a plurality of cell blocks (121 SIMILAR 12n) operatively connected to the AND array and OR array and provided for each of the plurality of external terminals, each receiving two output signals (OR1,OR2) from the OR array and outputting a signal to a corresponding external terminal based on the two output signals. By controlling an input/output of an input signal and an internally produced signal and a feedback thereof to the AND array, it is possible to realize various logic constitutions and develop a degree of freedom of the logic design in the entire device.
Inventors:
HIGUCHI MITSUO
OGURA KYONORI
SHINBAYASHI KOJI
NAKAOKA YASUHIRO
OGURA KYONORI
SHINBAYASHI KOJI
NAKAOKA YASUHIRO
Application Number:
JP12601488A
Publication Date:
October 30, 1996
Filing Date:
May 25, 1988
Export Citation:
Assignee:
FUJITSU KK
FUJITSU UI ERU ESU AI KK
FUJITSU UI ERU ESU AI KK
International Classes:
H03K3/037; H03K17/693; H03K19/173; H03K19/177; (IPC1-7): H03K19/177
Domestic Patent References:
| JP6264124A | ||||
| JP62114327A | ||||
| JP6323419A | ||||
| JP6313518A | ||||
| JP57132426A | ||||
| JP62144416A | ||||
| JP6330934A |
Other References:
【文献】米国特許4422072(US,A)
Attorney, Agent or Firm:
Aoki Akira (4 outside)