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Patent Searching and Data


Title:
NONVOLATILE SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPH0528778
Kind Code:
A
Abstract:

PURPOSE: To suppress the increase of a leak electric current and a punch through by a nonselection cell at a write time without degrading a write efficiency of a selection cell in a nonvolatile semiconductor memory.

CONSTITUTION: This nonvolatile semiconductor memory having a memory cell array arrayed in a matrix form memory cell transistors 11 having a laminated gate structure is constituted of source diffusion wirings 14 consisting of the diffusion layer wirings connected in common to the source of each cell transistor in the row direction of the cell array and the metallic wirings provided with one line ratio for one line or plural lines of a word line 12. And the memory is provided with source lines 15 electrically connected to the source diffusion wirings 14 selectively and a source decoder 8 giving a grounded potential to the source line connected to the source diffusion wirings 14 of the selected row of the cell array at a data write mode time.


Inventors:
ATSUMI SHIGERU
Application Number:
JP18656391A
Publication Date:
February 05, 1993
Filing Date:
July 25, 1991
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C16/02; G11C16/06; (IPC1-7): G11C16/06
Attorney, Agent or Firm:
Takehiko Suzue