Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH065818
Kind Code:
A
Abstract:
PURPOSE: To form a P-N diode between a drain of a TFT and a cell node of a base NMOS in a P-channel TFT load type SRAM memory cell.
CONSTITUTION: After an element isolation oxide film 2, an N-type polysilicon film 3, a silicon oxide film 4, a P-type polysilicon film 5, and a BPSG film 6 are formed on a silicon substrate 1, a connecting hole 7 is opened on the film 3 through the films 6, 5, 4, and a tungsten electrode 8 is buried therein. Since the film 5 and the electrode 8 are connected at the sidewall of the hole 7, the films 5, 3 can be connected without forming a P-N diode.
Inventors:
HAYASHI FUMIHIKO
Application Number:
JP16059092A
Publication Date:
January 14, 1994
Filing Date:
June 19, 1992
Export Citation:
Assignee:
NEC CORP
International Classes:
H01L27/11; H01L21/8244; H01L29/786; (IPC1-7): H01L27/11
Attorney, Agent or Firm:
Yosuke Goto (2 outside)
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