Title:
【発明の名称】プログラマブルロジックアレイ装置
Document Type and Number:
Japanese Patent JP2521943
Kind Code:
B2
Abstract:
PURPOSE:To balance the number of transistors and to improve the activity ratio of the transistors by providing short-circuit wirings between raws of a PLA unit, and selectively wiring limiting electrodes belonging to the raw of the unit through the wirings by second wiring group. CONSTITUTION:Short-circuit wirings 205 are provided between the raws of adjacent programmable logic array units (PLA units) 1, 4, and control electrodes 701, 702 belonging to the raws of the adjacent units 1, 4 are selectively wired through the short-circuit wirings 205 by second wiring groups 601-603. If the number of transistors to which input signals are supplied and the number of transistors to which an inverted signal of the input signal is supplied are apart from the ratio of 1:1, the control electrodes 701, 702 of the units 1, 4 can be wired by the wirings 205 and second groups 601-603. Thus, the activity ratio of the transistors of the units 1, 4 can be improved.
Inventors:
KOYABU KUNIHIRO
Application Number:
JP4346887A
Publication Date:
August 07, 1996
Filing Date:
February 25, 1987
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/82; H01L21/8234; H01L27/088; H01L27/112; H01L27/118; H03K19/177; (IPC1-7): H01L21/82; H01L21/8234; H01L27/088; H01L27/118
Attorney, Agent or Firm:
Seiichi Kuwai