Title:
INTER-PROCESSOR DATA COMMUNICATION METHOD
Document Type and Number:
Japanese Patent JP3003418
Kind Code:
B2
Abstract:
PURPOSE: To solve such problems as the transmission/reception synchronization, the overwriting, etc., when the working speed is increased with residence of the transmission/reception buffers at a main storage for the transmission and reception processes in a computer system where the nodes are connected together via a network.
CONSTITUTION: A function is provided to inform the physical address of a data receiving area of the receiver side to the transmitter side before the start of communication together with a function which suppresses the overwriting to the data receiving area with the double buffering of the receiver side, a function which secures the automatic synchronization among all nodes with the chained partial synchronization secured with the adjacent nodes, a function which gives an identifier to the data receiving area to inform the identifier to the transmitter side before the start of communication, transmits the data with addition of the identifier, compares two identifiers with each other at the receiver side, and produces an interruption to a processor for reception nodes if no coincidence is secured between both identifiers. In such a constitution, it is possible to attain a high speed inter-node data communication which is free from any copy produced between memories.
Inventors:
Masaaki Iwasaki
Hiroyuki Chiba
Naoki Utsunomiya
Koji Sonoda
Satoshi Yoshizawa
Masahiko Yamauchi
Hiroyuki Chiba
Naoki Utsunomiya
Koji Sonoda
Satoshi Yoshizawa
Masahiko Yamauchi
Application Number:
JP25615592A
Publication Date:
January 31, 2000
Filing Date:
September 25, 1992
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F13/00; G06F9/46; G06F13/38; G06F15/17; (IPC1-7): G06F15/177; G06F13/00
Attorney, Agent or Firm:
Yasuo Sakuta