Title:
【発明の名称】不揮発性メモリの使用方法
Document Type and Number:
Japanese Patent JP3075544
Kind Code:
B2
Abstract:
The present invention provides method for erasing a flash memory wherein "overerasing" can be prevented. To erase the cell, a gate voltage of 3 volts is applied to a control gate electrode and a voltage of 15 volts is applied to a source. A drain is left floating. At that time, the accumulated electrons begin to be injected from the floating gate to the source by tunneling. The threshold voltage of the flash memory cell decreases into less than 3 volts in the erasing operation, the potential difference between the floating gate and the source decreases. This enables the amount of charge by F-N tunneling to decrease and the erasing speed to decrease accordingly.
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Inventors:
Noriyuki Shimoji
Application Number:
JP11091392A
Publication Date:
August 14, 2000
Filing Date:
April 30, 1992
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
G11C17/00; G11C16/04; G11C16/14; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP6446297A | ||||
| JP57120296A | ||||
| JP3218066A | ||||
| JP589688A | ||||
| JP5259470A |
Attorney, Agent or Firm:
Furuya Eiko (2 outside)