PURPOSE: To activate a word line at high speed after a precharge period is released without being affected by increase even when the number of bits of an address signal line is increased, in an address decoder to which a precharge signal and an address signal with plural bits are inputted.

CONSTITUTION: This decoder is provided with a first gate circuit 31 to which the address signal with plural bits is inputted and a second gate circuit 32 to which the output of the first gate circuit 31 and a precharger signal Φ are inputted and whose output is connected to a word line Waj. The decoding of the address signal inputted to the first gate circuit 31 is ended within the precharge period, and the output is decided. Synchronizing with change in the precharge signal Φ, the word line Waj is activated by the second gate circuit 32.