Title:
CLOCK SYNCHRONIZING CIRCUIT
Document Type and Number:
Japanese Patent JP2560979
Kind Code:
B2
Abstract:
PURPOSE: To prevent the deterioration of an equalization characteristic caused by clock step-out in a demodulating equipment provided with a decision feedback type equalizer.
CONSTITUTION: In a pre-stage of a phase comparator 5, an automatic gain control amplifier 4 is provided. Therefore, deterioration of a clock component level in an output of a band pass filter 2 at the time of selective fading is corrected, and it becomes the same level as that of a stationary time. Also, at the stationary time, deterioration of a signal caused by an increase of the clock component level is prevented, and at the time of selective fading, step-out caused by deterioration of the clock component level is prevented. As a result, the equalizing capacity of a decision feedback type equalizer can be displayed enough.
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Inventors:
BABA SATOSHI
Application Number:
JP15190593A
Publication Date:
December 04, 1996
Filing Date:
June 23, 1993
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H03L7/00; H04B3/14; H04L7/00; H04L7/033; H04L27/22; (IPC1-7): H04L7/00; H03L7/00; H04B3/14; H04L27/22
Domestic Patent References:
| JP55117338A | ||||
| JP63156460A | ||||
| JP4157836A |
Attorney, Agent or Firm:
Yosuke Goto (2 outside)