【発明の名称】集積回路実装構造体

Japanese Patent JP2575734

B2

A high speed, high performance integrated circuit packaging structure that may be used for emulating wafer scale integration structures. The preferred embodiment comprises an interposer (9) having a base substrate having alternating insulation and conductive layers thereon, wherein a plurality of the conductive layers are wiring means which are adapted for maintaining an extremely low noise level in the package. The low noise level and low resistance and capacitance of the wiring means allows a plurality of discrete semiconductor segments (32) to be mounted on and interconnected by the integrated circuit package with a significantly reduced number of drivers and receivers than required by Rent's Rule. Each integrated circuit structure (9) of the present invention emulates a large chip or wafer scale integration structure in performance without having to yield the large chip or wafer, and without redundancy schemes. A plurality of these integrated circuit packaging structures (9) are combined by decals (29, 31) to form a central processing unit (1) of a computer or a portion thereof. In an alternate preferred embodiment, the base substrate of the interposer is made of silicon and any required drivers are formed therein, thus substantially eliminating the need for any drivers on each of the discrete semiconductor segments (32).

JP2011199320	SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF
JPS63150944	MANUFACTURE OF SEMICONDUCTOR DEVICE
JP4537702	Semiconductor devices and their manufacturing methods

SUKOTSUTO ROORENSU JAKOBU
PAAUETSU NIHARU
BAHAN OZUMATSUTO
HENRI DANIERU SHIINAAMAN

JP23273887A

January 29, 1997

September 18, 1987

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INTAANASHONARU BIJINESU MASHIINZU CORP

H01L23/52; H01L23/538; H01L27/00; (IPC1-7): H01L23/522; H01L23/52; H01L27/00

JP558096A

【文献】伊藤健一著「アースと雑音-こうすればノイズはこわくない」昭和49年4月30日,日刊工業新聞社発行,第43頁図3・15

Kiyoshi Goda (3 others)

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