Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP3057836
Kind Code:
B2
Abstract:
A static type random access memory device supplies current from a load circuit (120) to a selected digit line pair (D0/ CD0) in a write-in phase of operation, and the load circuit comprises a first pair of charging transistors (Qp25/ Qp28) coupled between a positive power voltage line (Vdd) and the selected digit line pair in a read-out phase, and a second pair of charging transistor (Qp26/ Qp27) also coupled between the positive power voltage line and the selected digit line pair and responsive to differential voltage indicative of a write-in data bit for selectively coupling one of the digit lines with the positive power voltage line so that the impedance of the load circuit is appropriately adjustable between the read-out phase and the write-in phase.
Inventors:
Hiroyuki Takahashi
Application Number:
JP23230591A
Publication Date:
July 04, 2000
Filing Date:
August 19, 1991
Export Citation:
Assignee:
NEC
International Classes:
G11C11/417; G11C11/409; G11C11/419; (IPC1-7): G11C11/417
Domestic Patent References:
| JP2183492A | ||||
| JP6344399A | ||||
| JP6476491A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)