Title:
METHOD FOR CONTROLLING PROCESSOR
Document Type and Number:
Japanese Patent JP2522176
Kind Code:
B2
Abstract:
PURPOSE: To obtain effective prefetch technique for a processor adopting a continuous buffer or the like by means of a simple hardware constitution by previously prefetching an instruction string pointed out by an instruction painter stored in the continuous buffer to a high speed buffer memory.
CONSTITUTION: A prefetching device 150 prereads continuation to be executed in the future from the continuous buffer 120 based upon continuation prereading information 123 and prefetches a necessary instruction or data by means of the continuation. An instruction pointer 227-1 out of the continuation preread based upon the information 123 is transferred to a high speed buffer memory monitoring part 211 in an instruction prefetching part 210. The monitoring part 211 inspects whether a buffer memory line including an instruction specified by the painter 227-1 is included in the high speed buffer memory or not based upon high speed buffer memory inspecting information 152. When the memory line is not included, a prefetch request issuing part 212 issues a prefetch request for the buffer memory line.
Inventors:
MOTOMURA MASATO
Application Number:
JP20146993A
Publication Date:
August 07, 1996
Filing Date:
August 13, 1993
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F9/38; G06F9/46; G06F12/08; (IPC1-7): G06F9/38; G06F12/08
Attorney, Agent or Firm:
Shinsuke Honjo