DATA-SIGNAL COMPENSATION DEVICE USED IN RECEIVER

Title:

DATA-SIGNAL COMPENSATION DEVICE USED IN RECEIVER

Document Type and Number:

Japanese Patent JPH0653941

Kind Code:

A

Abstract:

PURPOSE: To remove fluctuation in an AC level and DC offset, which are contained in a reception signal, by using three control loops and one branch selection switch circuit. CONSTITUTION: An outer control loop contains an adder 201, ADC 207, an amplifier 243, an adder 241, a delay device 237, DAC 245 and a switch 251. The DC voltage level of either data input signal 115 or 117 is compensated. An outer control loop contains a symbol slicer 235, an adder 233, an amplifier 219, an adder 217, a delay device 215, a limitter 213 and an adder 211, and it prevents pseudo synchronism. An automatic gain loop (AGC) controls the gain of a signal inputted to the slicer 235. The three loops remove the unnecessary AC level fluctuation and DC offset of the selected received input signal before the slicer 235. A diversity selection circuit generates a branch selection signal 127 selecting either reception signal.

Inventors:

DEBITSUDO JII KAASON
RUISU JIEI BUANATSUTA
CHIYAARUZU CHIYOI
DEERU EFU BENSON
JIEIMUZU SHII BEIKAA

Application Number:

JP32470092A

Publication Date:

February 25, 1994

Filing Date:

November 11, 1992

Export Citation:

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Assignee:

MOTOROLA INC

International Classes:

H04B1/10; H04B7/02; H04B7/08; H04L1/00; H04L27/22; (IPC1-7): H04L1/00; H04B1/10; H04B7/02

Attorney, Agent or Firm:

Shinsuke Onuki (1 person outside)

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