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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH053292
Kind Code:
A
Abstract:

PURPOSE: To realize effective integration of a longitudinal PNP transistor and a DMOSFET which are suitable for an n-channel MOSFET and an output step inverter circuit.

CONSTITUTION: First and second epitaxial layers 17, 18 are formed on a substrate 16, an N+-type buried layer 19 is formed on a surface of the substrate 16 and a P+-type collector buried layer 28 is formed on a surface of the first epitaxial layer 17. A P+-type emitter region 30 is formed on a surface of a region which becomes a base as a longitudinal PNP transistor 12. A body region 33 of a P+-type diffusion 32 is formed simultaneously with the P+-type emitter region 30. A P-type channel region 34 is formed integrally with the P+-type body region 33, and an N+-type source region 35 and a gate electrode 36 are formed as a DMOSFET 13. A P+-type buried layer 38 of an nMOSFET 11 is formed simultaneously with the collector buried layer 28 of the longitudinal PNP transistor 12.


Inventors:
OKODA TOSHIYUKI
Application Number:
JP15483291A
Publication Date:
January 08, 1993
Filing Date:
June 26, 1991
Export Citation:
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Assignee:
SANYO ELECTRIC CO
International Classes:
H01L27/06; H01L21/8249; H01L27/04; H01L29/78; (IPC1-7): H01L27/06
Attorney, Agent or Firm:
Takuji Nishino



 
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