PURPOSE: To extend the line set between a bus connected to a DSU and plural terminals and to attain the free arrangement of terminals in an INS network 64.

CONSTITUTION: The frame sent from a DSU 2 is sent as it is to the terminal side. When a frame synchronizing bit is detected out of the frame, a 5-bit shift circuit 19 performs the 5-bit shift. Meanwhile the return frame data sent from plural memories through plural terminals are simultaneously read out and sent back to the DSU 2 in response to the end output of the bit shift. Thus the terminals are freely arranged regardless of the line length. Then the timing errors if caused among the frame data returned to the DSU 2 from each terminal can be absorbed. As a result, the occurrence of the data transfer errors can be prevented.