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Patent Searching and Data


Title:
FRAME SYNCHRONIZATION DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPH0537512
Kind Code:
A
Abstract:

PURPOSE: To simplify the circuit configuration.

CONSTITUTION: A frame data inputted to a terminal 13 is recovered into a CMP signal to be logic 'H' in a n-th multi-frame by a frame coincident point detection circuit 1 and the signal enters a ROM 6. On the other hand, a protective stage number is changed by a selector signal M in order to implement synchronization protection in response to various multiplex systems. A (n+/≠n-) signal and a (OK+/NG-) signal are sent from the ROM 6 to a ROM 3 and a frame synchronization point is detected from the inputted frame data.


Inventors:
NISHIMURA YASUYO
SUZUKI YOSHIAKI
Application Number:
JP21324191A
Publication Date:
February 12, 1993
Filing Date:
July 31, 1991
Export Citation:
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Assignee:
NEC CORP
NEC SHIZUOKA LTD
International Classes:
H04J3/06; H04L7/08; (IPC1-7): H04J3/06; H04L7/08
Attorney, Agent or Firm:
Masaki Yamakawa