PURPOSE: To turn the main part of state fluctuation detection such as a data comparison processing system and the write processing system of state fluctuation data to hardwares and to accelerate a state fluctuation detection processing.

CONSTITUTION: Data simultaneously read from two memories 16 and 17 are respectively sent to a comparator circuit 19 and the compared result of the comparator circuit 19 is inputted to an address counter 20. The address counter 20 subscribes latest address information on an address bus 14 to an address indicated by the latest address information in a second memory 18 as long as data noncoincidence is not detected by the comparator circuit 19. Also, when the data noncoincidence is detected, an address value is increased by one and outputted to the second memory 18 and a memory write signal 37 is outputted to the second memory 18 at a prescribed timing after the detection. Simultaneously, the connection destination of the data input terminal of the second memory 18 is switched to the side of a data bus 15. Thus, noncoincident data on the data bus 15 are written on the second memory 18 following the address information of the noncoincident data.