PURPOSE: To increase a capacity of a memory cell of a ROM by preventing a miniaturization of a pattern and an increase in an area of a chip.

CONSTITUTION: An N-type impurity region 11 to become a bit line is formed on a silicon substrate 10, and a polycrystalline silicon electrode 13 to become a word line is formed across the region 11 on an oxide film 12 covering the region 11. Further, a polycrystalline silicon layer 15 is formed on an oxide film 14 covering the electrode 13, and an N-type impurity region 16 to become a big line is formed across the electrode 13 in the layer 15. A memory cell transistor of a lower layer side is formed of the electrode 13 and the region 11 in the substrate 10, and a memory cell transistor of an upper layer side is formed of the electrode 13 and the region 16 in the layer 15.