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Title:
BIMOS INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPH0590508
Kind Code:
A
Abstract:

PURPOSE: To prevent the electric continuity of a parasitic transistor and the generation of an excessive current when noise permeates into an MOS circuit part, by forming a buried layer of the MOS circuit part so as to have impurity concentration which is higher than an epitaxial layer, in common to a plurality of transistors, and lower than a buried layer of a bipolar circuit part.

CONSTITUTION: When the impurity concentration of a buried layer in an MOS circuit part is different from a layer for a bipolar circuit part use, high impurity concentration is adopted because a buried layer 11 of a bipolar circuit part decreases the collector resistance of a transistor 20. The impurity concentration of an N-type buried layer 12 of the MOS circuit part is set to be lower than the above high impurity concentration by about one figure. When the buried layer is isolated for each MOS transistor and formed so as to have the same impurity concentration as the buried layer in the bipolar circuit part, the mutal intervals of buried layers 13 are set to be larger than or equal to twice the thickness of an epitaxial layer 2. Thereby a noise current is restrained, and the malfunction and the damage of an internal junction when noise permeates into a BiMOS integrated circuit device can almost completely be prevented.


Inventors:
SASAKI OSAMU
TADA HAJIME
Application Number:
JP24994191A
Publication Date:
April 09, 1993
Filing Date:
September 30, 1991
Export Citation:
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Assignee:
FUJI ELECTRIC CO LTD
International Classes:
H01L27/06; H01L21/8249; (IPC1-7): H01L27/06
Attorney, Agent or Firm:
Iwao Yamaguchi



 
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