PURPOSE: To speed up the static delay analysis processing.

CONSTITUTION: Information related to circuit elements and connection between them are stored in a circuit information storage part 1. A stage-number giving part 2 obtains the number of terminal stages from the start point of a path as the delay analysis object with respect to all terminals in the circuit based on information stored in the circuit information storage part 1. A stage-number information storage part 3 stores the number of terminal stages of each of all terminals in the circuit obtained by a stage-number giving part 2 correspondingly to each of all terminals. An assignment part 4 assigns terminals based on the number of terminal stages of each of all terminals in the circuit stored in the stage-number information storage part 3 so that terminals having the same number of stages are approximately uniformly assigned to plural processors. Consequently, the occurrence of the wait time in a specific processor is reduced, and a high-parallel and high-speed processing is enabled.