Title:
FIELD PROGRAMMABLE GATE ARRAY
Document Type and Number:
Japanese Patent JP3072887
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To define a user logic circuit with a larger scale by improving the operating efficiency of components such as transistors(TRs).
SOLUTION: TRs M5, M6, M11, M12 are turned on/off depending on inputs. The logic is defined by series connection and parallel connection. Outputs of plural logic arithmetic systems defined with a prescribed logic by the path TRs M5, M6, M11, M12 are given to a 3-input AND logic gate G being a multi- input CMOS logic circuit. The logic is defined by writing an on-state to F61-F67, F81-F85, and anti-fuses. Through the constitution of the path TR logic circuit part of the logic arithmetic circuit and the multi-input CMOS logic circuit as above, the user logic circuit is effectively defined so as to improve the operating efficiency of components such as TRs.
Inventors:
Norimitsu Sako
Application Number:
JP32149395A
Publication Date:
August 07, 2000
Filing Date:
December 11, 1995
Export Citation:
Assignee:
Kawasaki Steel Co., Ltd.
International Classes:
H03K19/173; H03K19/177; (IPC1-7): H03K19/177; H03K19/173
Domestic Patent References:
| JP964283A | ||||
| JP627202A | ||||
| JP73838B2 | ||||
| JP73837B2 | ||||
| JP6506098A |
Attorney, Agent or Firm:
Satoshi Takaya (2 outside)