Title:
【発明の名称】半導体論理回路
Document Type and Number:
Japanese Patent JP2544732
Kind Code:
B2
Abstract:
PURPOSE:To easily and exactly set the delay interval of a delaying circuit by providing the delaying circuit on an AND circuit side, and allowing it to have the same characteristic as that of the AND circuit against the fluctuation of an operating condition. CONSTITUTION:A conventional signal transfer use gate circuit is replaced with a signal transfer gate circuit 30A constituted of only an AND gate except a delaying circuit, and a delaying circuit 100 is provided on an AND circuit 20 side. This circuit 100 is provided with a PMOS 101 by which a power supply voltage VDD and a clock pulse phi are applied to the source and the gate, respectively, and to the drain of its PMOS 101, a signal line 102 is connected. To this signal line 102, drains of NMOSs 103-1, 103-2 are connected. In this case the NMOSs 103-1, -2 are combined so that one of them becomes a high level in a signal propagation period. Also, as for the signal line 102, capacities 104-1, -2 of delay elements are connected to the intersection part of signal lines 21-3, -4, respectively, and also, the signal line 102 is connected to the AND gate 32 of the signal transfer gate circuit 30A through an inverter 105.
Inventors:
MORI TOSHITAKA
Application Number:
JP951887A
Publication Date:
October 16, 1996
Filing Date:
January 19, 1987
Export Citation:
Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H03K19/0175; G06F7/00; G11C17/18; H01L21/82; H01L27/10; H03K19/177; (IPC1-7): H03K19/177; G11C17/18; H01L21/82; H01L27/10; H03K19/0175
Domestic Patent References:
| JP6020632A | ||||
| JP60233933A | ||||
| JP61101124A | ||||
| JP5999823A |
Attorney, Agent or Firm:
Kakimoto Kyosei