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Title:
POWER SUPPLY CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
Japanese Patent JPH0660653
Kind Code:
A
Abstract:

PURPOSE: To prevent dielectric breakdown by limiting the upper limit of high voltage output based on decision result of power supply voltage thereby stabilizing the output voltage.

CONSTITUTION: When power supply voltage is lower than a level determined arbitrarily based on the number of stages and threshold levels of MOSTr Q3-Qn, word line potential is clamped at the threshold value of n-channel MOSTr M3-M5 through a word line potential generating circuit 40. If the power supply voltage is stepped up when fluctuation of power supply voltage exceeds a set value, word line potential increases excessively and may cause dielectric breakdown of a storage cell transfer MOS. In order to avoid the situation, an inverter circuit 12 is inverted and one input terminal of a NAND circuit in the word line potential generating circuit 40 is pulled Low thus stopping operation of a high voltage generating circuit 41. Consequently, a p-channel MOSTr M7 is turned ON and power supply voltage Vdd is fed to the output node of the circuit 41. This constitution prevents dielectric breakdown of storage cell transfer MOS in a storage cell array.


Inventors:
MAEDA TOSHIO
NAKAMOTO TOSHIHIRO
Application Number:
JP23655092A
Publication Date:
March 04, 1994
Filing Date:
August 12, 1992
Export Citation:
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Assignee:
HITACHI LTD
HITACHI DEVICE ENG
International Classes:
G11C11/407; H02M3/00; H02M3/07; (IPC1-7): G11C11/407; H02M3/00; H02M3/07
Attorney, Agent or Firm:
Tamamura Shizuyo



 
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