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Title:
THROUGH CURRENT PREVENTING CIRCUIT
Document Type and Number:
Japanese Patent JPH0541647
Kind Code:
A
Abstract:

PURPOSE: To obtain the through current preventing circuit preventing the generation of the through current and suppressing the increase of the power consumption.

CONSTITUTION: The through current preventing circuit is provided with a P transistor P1x inputting a first signal to a gate to be serially connected between high potential power source VDD line and low potential power source VSS line, a P transistor P1c inputting a second signal to the gate, N transistor N1c inputting the second signal to the parallely connected gate, N transistor N1x inputting the first signal to the gate, NOR gate 3 connecting the N transistor N1c inputting the second signal to the parallely connected gate and the N transistor M1x inputting the first signal to the gate in order, N transistor N1c parallely connecting the P transistors P1x and P1c, and inverter 2 taking the contact between the N transistor N1c parallely connected with the P1c and the N1x as an input terminal.


Inventors:
IMAI KAZUHIKO
Application Number:
JP15338191A
Publication Date:
February 19, 1993
Filing Date:
June 25, 1991
Export Citation:
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Assignee:
FUJITSU LTD
FUJITSU VLSI LTD
International Classes:
H03K17/16; (IPC1-7): H03K17/16
Attorney, Agent or Firm:
Teiichi



 
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