Title:
【発明の名称】集積半導体回路
Document Type and Number:
Japanese Patent JP2520857
Kind Code:
B2
Abstract:
An integrated semiconductor circuit includes a substrate; a layer of electrical structures disposed in the substrate; conductor runs connected to the electrical structures; at least one electrically conducting surface element covering part of the electrical structures, part of the substrate and part of the conductor runs defining first conductor runs covered by the at least one surface element and second conductor runs; an insulating layer electrically separating the at least one surface element from first the conductor runs; and a passivating layer covering the substrate, the electrical structures, the conductor runs and the at least one surface element; the at least one surface element having at least the same thickness and the same chemical properties as the conductor runs; and the passivating layer being at least as thick above the at least one surface element covering the first conductor runs as above the second conductor runs.
Inventors:
HARUTOMUUTO SHURENKU
Application Number:
JP24940686A
Publication Date:
July 31, 1996
Filing Date:
October 20, 1986
Export Citation:
Assignee:
SIEMENS AG
International Classes:
H01L21/822; G06F21/75; G06F21/86; G06K19/073; G06K19/077; H01L21/3205; H01L21/8247; H01L23/52; H01L23/58; H01L27/04; H01L29/788; H01L29/792; (IPC1-7): H01L21/3205; H01L21/822; H01L21/8247; H01L27/04; H01L29/788; H01L29/792
Domestic Patent References:
| JP5232270A | ||||
| JP5562764A | ||||
| JP60187038A | ||||
| JP130304B2 |
Attorney, Agent or Firm:
Tomimura Kiyoshi