PURPOSE: To provide a parallel adder capable of reducing a chip area by constituting a carry generating and transmitting block and a summing block of a transmission gate so as to simplify a circuit and to simultaneously improve a velocity.

CONSTITUTION: A carry generating and transmitting block 20, a carry evaluation block 21 and a summing block calculating a final sum 22 are provided and the blocks 20 and 22 are constituted of the transmission gate to calculate addition only by five levels. For example, the carry generation circuit of the block 20 is provided with an inverter 25 for inverting an input signal B1 and a CMOS transmission gate 26 for transmitting an input signal A2 in response to an input signal and the inverted input signal B1 and an NMOS transmission gate 27 for transmitting the input signal in response to the inverted input signal. Consequently, an additional delay time is reduced by reducing the adding levels of an old adder from eight to five levels.