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Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES
Document Type and Number:
Japanese Patent JPH0738099
Kind Code:
A
Abstract:

PURPOSE: To make it possible to realize a one-sided LDD structures MOS transistor in one ion implantation step and without forming a side wall by forming drain side surface of the gate electrode with a slanting shape and forming a low concentration region below the slanted part by ion implantation.

CONSTITUTION: Particularly in a MOS transistor with the LDD structure, the gate electrode 3 is formed on the semiconductor substrate 1 via the insulating film 2. Next, the resist mask 10 is formed with the same pattern as the gate electrode 3, and the temporary data electrode 11a is formed by anisotropic etching in the vertical direction after masking the resist mask 10. Next, the gate electrode 11 is formed by anisotropic etching in the slating direction on the drain side in the direction a shown in the figure. After removing the resist mask 10, high concentration ion implantation is done over the entire area from the above. Because of this, the impurity region 8a that acts as the source and the impurity area 8b that acts as the drain can be formed with the same impurity concentration.


Inventors:
YAGI TAKASHI
Application Number:
JP17670693A
Publication Date:
February 07, 1995
Filing Date:
July 16, 1993
Export Citation:
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Assignee:
KANSAI NIPPON ELECTRIC
International Classes:
H01L21/265; H01L21/336; H01L29/78; (IPC1-7): H01L29/78; H01L21/265; H01L21/336



 
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