Title:
SEMICONDUCTOR STORAGE INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3036411
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make redundancy access do not limit address access and to reduce a chip area by arranging a redundancy fuse circuit on the position so that a wiring length between the redundancy fuse circuit and a redundancy cell array becomes minimum.
SOLUTION: The redundancy cell arrays 30-32 are arranged on plural memory cell arrays 20-23, and the redundancy fuse circuit 80-82 corresponding to them are arranged in parallel to the redundancy arrays. When a fault address is selected, a redundancy decision signal RDN stops all sense amplifier controllers 40-44. A redundancy signal RED1 selects a redundancy word driver 51 and the sense amplifier controllers 41, 42, actuates the sense amplifier controllers 41, 42 which were once stopped, by the signal RDN to select the redundancy cell array 30.
Inventors:
Kyouichi Nagata
Application Number:
JP26891495A
Publication Date:
April 24, 2000
Filing Date:
October 18, 1995
Export Citation:
Assignee:
NEC
International Classes:
H01L21/82; G11C11/401; G11C29/00; G11C29/04; H01L27/10; (IPC1-7): G11C29/00; H01L21/82; H01L27/10
Domestic Patent References:
| JP4252500A | ||||
| JP628888A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)
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