Title:
THREE-DIMENSIONAL DIRECT WRITING EEPROM ARRAY AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPH065824
Kind Code:
A
Abstract:
PURPOSE: To manufacture an integrated circuit with the maximum circuit density by providing at least two vertical type direct writing EEPROM cells, that are paired each in at least one control gate in a trench that is formed in a semiconductor substrate. CONSTITUTION: A shallow trench 30 with dimensions and a configuration for accommodating at least one three-dimensional direct writing EEPROM memory cell 34 is formed in a substrate material 32, and a continuous recall gate RG is arranged at the bottom of each trench 30. Also, a discontinuous floating gate FG is provided along two sidewall parts of each trench 30, and at the same time, a program gate PG is provided at the upper part of each trench 30, thus demarcating the EEPROM cell 34 by the gates FG, RG, and PG. The program PG is mutually connected via a control gate (word line) that runs at a right angle to the trench 30. Then, a common (N<+> ) diffused region 42 is provided between the trenches 30 in the substrate 32.
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Inventors:
KUROODO RUI BERUTAN
DONETSURI JIYOOZEFU DEI MARIA
MIYAGAWA KIYOSHI
SAKAGAMI YOSHIISA
DONETSURI JIYOOZEFU DEI MARIA
MIYAGAWA KIYOSHI
SAKAGAMI YOSHIISA
Application Number:
JP3215193A
Publication Date:
January 14, 1994
Filing Date:
February 22, 1993
Export Citation:
Assignee:
IBM
International Classes:
H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JPS62269363A | 1987-11-21 |
Attorney, Agent or Firm:
Koichi Tonmiya (4 outside)
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