Title:
【発明の名称】半導体集積回路
Document Type and Number:
Japanese Patent JP3082091
Kind Code:
B2
Abstract:
PURPOSE:To prevent malfunction by providing a p-channel MOS transistor to individually pull-up drive an n-channel MOS transistor on the lower-step side. CONSTITUTION:A multi-input logic circuit 1 is formed by connecting a common pull-up circuit 11 to the highest step of plural n-channel MOS transistors N1, N2 and N3 which are serially cascade-connected. The MOS transistors N2 and N3 in the lower step side are respectively individually pull-up driven when a logical output A rises from L to H by p-channel transistors P2 and P3. Therefore, the load of the pull-up circuit 11 when raising the logical output A from L to H is reduced, the rise of the logical output A is selectively accelerated, and the characteristic is balanced for rise and fall. Thus, erroneous write or erroneous read caused by double selection can be prevented.
Inventors:
Kazuki Homma
Kinya Mitsumoto
Kinya Mitsumoto
Application Number:
JP19685990A
Publication Date:
August 28, 2000
Filing Date:
July 25, 1990
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G11C11/418; G11C11/407; G11C11/41; G11C11/413; H03K19/003; H03K19/0948; (IPC1-7): G11C11/41; G11C11/413; G11C11/418; H03K19/003; H03K19/0948
Domestic Patent References:
| JP6358696A | ||||
| JP1149289A |
Attorney, Agent or Firm:
Tomio Ohinata