PURPOSE: To reduce the pattern area of a VLSI of an input/output device and at the same time to secure the use of both clock synchronous and asynchronous types.

CONSTITUTION: A FIFO 5 containing an output data line 6a and an input data line 6c is provided together with a transmission register 3 which transmits the data to a network N, a reception register 4 which receives the data from the network N, a control data output means 1 which stores the control data 1a and 1b, a 1st data switch circuit 2a which receives the input of the date 18 and connects a data bus 8 or the line 6a to the register 3, and a 2nd data switch circuit 2b which receives the input of the data 1b and connects the bus 8 or the line 6c to the register 4. In such a constitution, the switch is carried out among a mode where the FIFO 5 is connected to the register 3, a mode where the FIFO 5 is connected to the register 4, and a mode where the FIFO 5 is connected to both registers 3 and 4 respectively based on the set value of a mode register 1.