Title:
装置間接続を組み込むニューラルネットワークプロセッサ
Document Type and Number:
Japanese Patent JP7108268
Kind Code:
B2
Abstract:
A novel and useful neural network (NN) processing core incorporating inter-device connectivity and adapted to implement artificial neural networks (ANNs). A chip-to-chip interface spreads a given ANN model across multiple devices in a seamless manner. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level. Dynamic resource assignment agility is provided which can be adjusted as required depending on resource availability and capacity of the device.
Inventors:
Baum, avi
Danone, Oh
Zeitlin, Hudder
Dandelion
Fague, lami
Danone, Oh
Zeitlin, Hudder
Dandelion
Fague, lami
Application Number:
JP2019555011A
Publication Date:
July 28, 2022
Filing Date:
April 03, 2018
Export Citation:
Assignee:
HIRO Technologies Limited
International Classes:
G06N3/06
Domestic Patent References:
| JP1201764A | ||||
| JP2015536494A |
Foreign References:
| US20130073497 | ||||
| CN104809498A |
Other References:
CARRILLO, S. et al.,Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementation,Proceedings of 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip,2012年05月,pages 83-90
Attorney, Agent or Firm:
Ryoichi Takaoka
Nao Oda
Akiyo Iwahori
Kamoto Takahashi
Nao Oda
Akiyo Iwahori
Kamoto Takahashi