Title:
中性子変換層組み込み型半導体基板
Document Type and Number:
Japanese Patent JP2007516432
Kind Code:
A
Abstract:
A semiconductor substrate incorporating a neutron conversion layer (such as boron-10) that is sensitive enough to permit the counting of single neutron events. The substrate includes an active semiconductor device layer, a base substrate, an insulating layer provided between the active semiconductor device layer and the base substrate, and a neutron conversion layer provided between the active semiconductor device layer and the base substrate. The neutron conversion layer is located within the insulating layer, between the insulating layer and the base substrate or between the active semiconductive device layer and the insulating layer. A barrier layer is provided between at least one of the neutron conversion layer and the active semiconductor device layer and the neutron conversion layer and the base substrate to prevent diffusion of the neutron conversion material provided in the neutron conversion layer. Further, a plurality of trenches may be formed in the active semiconductor device layer. In such a case, a trench neutron conversion layer is formed in at least one of the trenches to improve device sensitivity.
Inventors:
Hughes, Harold, Elle.
Application Number:
JP2006536647A
Publication Date:
June 21, 2007
Filing Date:
September 28, 2004
Export Citation:
Assignee:
THE UNITED STATES OF AMERICA
International Classes:
G01T3/08; H01L27/12; H01L27/14; H01L29/84; H01L31/0248; H01L31/08; H01L31/115; H01L27/10
Domestic Patent References:
| JPH05281364A | 1993-10-29 | |||
| JPH05150051A | 1993-06-18 | |||
| JPH0247580A | 1990-02-16 | |||
| JPH06180370A | 1994-06-28 |
Foreign References:
| WO1997023003A1 | 1997-06-26 | |||
| US6075261A | 2000-06-13 |
Attorney, Agent or Firm:
Taro Yaguchi
Yasuaki Yamaguchi
Yasuaki Yamaguchi