Title:
DMA TRANSFER CONTROLLER
Document Type and Number:
Japanese Patent JP3204297
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent bus transfer on an inside bus at the time of DMA transfer from being made exclusive, and to attain simultaneous memory transfer in mutual directions.
SOLUTION: In this device, access through a general bus 20 to storage devices 16 and 17 is controlled by a bus controller 2, and DMA read for transferring data from an outside system which is present outside the general bus 20 to the storage device and DMA write for transferring data from the storage device to the outside system is operated between the outside system and the storage device. In this case, this device is provided with a FIFO system memory 4 provided between a bus controller 2 and an inside bus 21 for inputting and outputting data synchronously with input and output through the general bus, inside bus controller 3 for controlling access through the inside bus 21 to the storage device, and control block equipped with an inside DMA bus through which access to the storage device is performed independently of the inside bus 21 at the time of the DMA write for controlling the DMA write and the DMA read.
Inventors:
Akira Nakamura
Application Number:
JP13534697A
Publication Date:
September 04, 2001
Filing Date:
May 26, 1997
Export Citation:
Assignee:
NEC
International Classes:
G06F13/28; (IPC1-7): G06F13/28
Domestic Patent References:
| JP52557A | ||||
| JP8221356A |
Attorney, Agent or Firm:
Nobuyuki Kaneda (2 others)