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Title:
NO OPERATION CONTINUING STEP INTRUCTING SYSTEM FOR ARITHMETIC PROCESSOR
Document Type and Number:
Japanese Patent JPH06168115
Kind Code:
A
Abstract:

PURPOSE: To continue no operation processing for a certain time without being affected by the processing speed of an arithmetic processor.

CONSTITUTION: An instruction code analyzing part 11 analyzes an instruction code, and an arithmetic clock counting part 12 controls the execution of no operation continuing step by the analysis result. A clock part 15 generates a standard clock for the operation of the arithmetic clock counting part 12. An arithmetic processor peculiar information setting and holding part 14 holds information peculiar to the arithmetic processor, and an execution part 13 is the execution part of the arithmetic processor. Thus, it is unnecessary to correct the timings of the arithmetic processor and an input/output device even if the capability of the arithmetic processor is improved.


Inventors:
SHIMIZU KATSUYUKI
Application Number:
JP31956392A
Publication Date:
June 14, 1994
Filing Date:
November 30, 1992
Export Citation:
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Assignee:
NEC SHIZUOKA LTD
International Classes:
G06F9/30; (IPC1-7): G06F9/30
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)



 
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