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Title:
NOISE COMPENSATING METHOD FOR SWITCHED CAPACITOR CIRCUIT
Document Type and Number:
Japanese Patent JPS62164309
Kind Code:
A
Abstract:

PURPOSE: To delete a parastic charge given from respective types of the noise source by fine-adjusting the capacity value of one capacitor or above for adjustment provided between a switching capacitor and a switching clock line.

CONSTITUTION: Respective types of the noise such as a crosstalk with other signal, an electric power source noise and a field through noise are equally displayed as an off-setting generating source by capacitors 8 and 9. At either or plural of capacitors 12, 13, 14 and 15 connected to clocks PH1 and PH2 and the reverse phase clocks PH1 and PH2, the charge in the reverse direction is accumulated by the same charge quantity as the charge of the capacitors 8 and 9, thereby, being able to delete the influence of the off-setting. Consequently, the capacity value, in which the charge sufficiently larger than the charging quantity thought to be accumulated at the capacitors 8 and 9 is accumulated, is assigned at the capacitors 12, 13, 14 and 15 beforehand, one side electrode of either of capacitors is composed of a metallic wiring such as aluminum of the integrating circuit, and the electrode part of respective capacitors are deleted by a laser beam, etc., little by little.


Inventors:
KODAIRA MITSUHARU
IIDA ATSUSHI
Application Number:
JP539086A
Publication Date:
July 21, 1987
Filing Date:
January 14, 1986
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
H03H19/00; (IPC1-7): H03H19/00
Domestic Patent References:
JPS56169413A1981-12-26
JPS57180221A1982-11-06
Attorney, Agent or Firm:
Kisaburo Suzuki (2 outside)



 
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