NOISE ELIMINATION CIRCUIT - MATSUSHITA ELECTRIC WORKS LTD

Title:

NOISE ELIMINATION CIRCUIT

Document Type and Number:

Japanese Patent JPH0653788

Kind Code:

A

Abstract:

PURPOSE: To reduce the cost by simplifying the configuration.

CONSTITUTION: The noise elimination circuit is a circuit eliminating a noise pulse whose pulse width is less than a prescribed pulse width, in which a 1st connecting point P1 is connected to an output of a 1st NOR circuit 1 and a 2nd connecting point P2 is connected to both inputs of a 2nd NOR circuit 2 and one input of a 3rd NOR circuit 3. Furthermore, a 3rd connecting point P3 is connected to an output of the 2nd NOR circuit and a 4th connecting point P4 is connected to the other input of the 3rd NOR circuit. Then the output of the 3rd NOR circuit is connected to one input of the 1st NOR circuit, the other terminal of a 1st capacitor C1 and the other terminal of a 2nd capacitor C2 connect to a signal earth, the other input of the 1st NOR circuit is used for a noise elimination input Bin and an output of the 3rd NOR circuit is used for a noise elimination output BOUT.

Inventors:

TSUTSUI JOJI

Application Number:

JP20133992A

Publication Date:

February 25, 1994

Filing Date:

July 28, 1992

Export Citation:

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Assignee:

MATSUSHITA ELECTRIC WORKS LTD

International Classes:

G08B13/191; H03K5/01; H03K5/1252; (IPC1-7): H03K5/01; G08B13/191

Attorney, Agent or Firm:

Mikio Kawase (1 person outside)

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