Title:
ノイズシェーピング・デジタル周波数合成
Document Type and Number:
Japanese Patent JP4620931
Kind Code:
B2
Abstract:
A clock generator for automatic test equipment employs an improved technique for generating clock signals from a reference clock. To generate a desired clock signal, a clock generator produces a time-quantized signal having a period equal to an integer number of reference clock periods and equal to the desired clock period, plus or minus a quantization error. For each cycle of the desired clock signal, a noise-shaping requantizer processes the quantization error to generate noise-shaping signals. The noise-shaping signals then establish delay values of a variable pipeline delay. The variable pipeline delay adjusts each period of the time-quantized signal by an integer number of reference clock cycles, based upon the noise-shaped signals. The effect of noise shaping the quantization error and selectively delaying the time-quantized signal is to shift jitter in the time-quantized signal from relatively low frequencies to relatively high frequencies. A phase-locked loop can then be used to filter the remaining high-frequency jitter.
Inventors:
Shane, Timothy W
Application Number:
JP2002521678A
Publication Date:
January 26, 2011
Filing Date:
August 01, 2001
Export Citation:
Assignee:
TERADYNE INCORPORATED
International Classes:
H03B28/00; H03K5/00; G06F1/025; H03L1/00; H03L7/081; H03L7/16; H03M3/02
Domestic Patent References:
| JP11145828A |
Attorney, Agent or Firm:
Kazuo Shamoto
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Otsuka Naruhiko
Tadashi Masui
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Otsuka Naruhiko