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Title:
NOISE SUPPRESSION CIRCUIT
Document Type and Number:
Japanese Patent JP2003338722
Kind Code:
A
Abstract:

To suppress noise over a wide frequency range.

A noise suppression circuit 1 suppresses noise generated by an electronic device 2 and propagated on conductive lines 3a and 3b. The noise suppression circuit 1 is provided with a low-noise reduction circuit 10 and a high-noise reduction circuit 80. The low-noise reduction circuit 10 is connected to the electronic device 2 via the conductive lines 3a and 3b. The high-noise reduction circuit 80 is serially connected to the low noise reduction circuit 10 and is connected to conductive lines 4a and 4b of a power source line 4. The high-noise reduction circuit 80 is provided with a detection circuit for detecting a common mode noise propagated on the conductive lines 3a and 3b, a negative phase signal generation circuit for generating a negative phase signal, having a negative phase of noise detected by the detection circuit, and an injection circuit for injecting the negative phase signal generated to the conductive lines 3a and 3b by the negative phase signal generation circuit.


Inventors:
WAZAKI MASARU
SAITO YOSHIHIRO
Application Number:
JP2002144817A
Publication Date:
November 28, 2003
Filing Date:
May 20, 2002
Export Citation:
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Assignee:
TDK CORP
International Classes:
H03H1/00; H03H7/09; H02M1/12; (IPC1-7): H03H7/09; H02M1/12
Attorney, Agent or Firm:
Katsumi Hoshimiya



 
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