PURPOSE: To prevent an output clock from instantaneous interruption even if any one input clock is interrupted at a high level or a low level by combining plural AND circuits and NAND circuits to constitute OR and exclusive OR circuits.

CONSTITUTION: If one input clock, e.g. CLKB, is interrupted at the high level, high level clock interruption of one period is generated in an output clock CLKY from a NAND circuit IC5. However, the output clocks CLKA', CLKB' of NAND circuits IC3, IC4 are inconsistent each other during said period, so that the output of an exclusive OR circuit IC7 is in the high level, the output of an AND circuit IC8 is turned to the low level and the output of a NAND circuit IC9 is turned to the low level. Consequently, the output of an AND circuit IC6 is inverted and an output clock CLKZ is prevented from clock interruption at the high level.