Title:
不揮発性メモリテスト構造および方法
Document Type and Number:
Japanese Patent JP2005518630
Kind Code:
A
Abstract:
The invention relates to a non-volatile memory test structure, comprising a plurality of memory cells arranged in rows and columns, each memory cell comprising at least a memory transistor and having a source terminal, a gate terminal and a drain terminal. In order to provide a fast and effective test structure to be used for fast reliability evaluation in monitoring of non-volatile memory elements on every wafer it is proposed according to the present invention that:-a group of said memory cells is connected in parallel,-the source terminals of the memory cells in the group are connected together and to a source line,-the drain terminals of the memory cells in the group are connected together and to a drain line,-the gate terminals of the memory cells in the group are connected together and to a gate line, and-said gate line has two connections to apply an electrical current to said gate line for using it as a heating means.
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Inventors:
Guokiao, Tao
Application Number:
JP2003572041A
Publication Date:
June 23, 2005
Filing Date:
January 31, 2003
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
G11C16/02; G11C16/04; G11C29/04; G11C29/06; G11C29/12; (IPC1-7): G11C29/00; G11C16/02; G11C16/04
Attorney, Agent or Firm:
Kenji Yoshitake
Masami Tamama
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki
Masami Tamama
Hidetoshi Tachibana
Yasukazu Sato
Hiroshi Yoshimoto
Yasushi Kawasaki