Title:
NON-VOLATILE MEMORY
Document Type and Number:
Japanese Patent JP3181046
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a non-volatile memory wherein a read-out margin is large, with a reliable read-out characteristics.
SOLUTION: Transistors of MFMIS structure are arrayed in matrix where a floating gate 4, ferroelectrics layer 5, and control gate 6 are sequentially laminated, through a gate insulating film 3, on the surface of a semiconductor substrate 1 between a source and drain regions formed on the semiconductor substrate. Here, the control gate is connected to a ward line, the source region is connected to a source line, and the drain region is connected to a drain line, while a floating line comprising a write-in gate so configured as to form a capacitor with the floating gate provided. The word line and the source line of the matrix in the same row are common-connected while the drain line and the floating line of the matrix in the same column are common-connected, with a source/drain voltage and a gate voltage allowed to be set independently.
Inventors:
Takakazu Fujimori
Application Number:
JP29133799A
Publication Date:
July 03, 2001
Filing Date:
October 13, 1999
Export Citation:
Assignee:
ROHM Co., Ltd.
International Classes:
H01L21/8247; G11C11/22; H01L21/8246; H01L27/10; H01L27/105; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L27/105; G11C11/22; H01L21/8247; H01L29/788
Domestic Patent References:
| JP897386A | ||||
| JP8264665A |
Attorney, Agent or Firm:
Tadashi Hagino (2 outside)