Title:
NON-VOLATILE MULTI-LEVEL MEMORY
Document Type and Number:
Japanese Patent JP3948547
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a non-volatile multi-level memory in which 3 bits/1 cell and defect relieving are realized with a simple circuit.
SOLUTION: In the non-volatile multi-level memory, storage information of 3 bits is stored in one memory cell and a different Y address is allotted to each bit, a first address signal for specifying each bit of one memory cell is used for an address signal of 2 bits formed of a counter of ternary, a second address signal selecting one memory cell is used for an address signal of a plurality of bits formed of a counter of binary receiving a carry signal of the counter of ternary as an input, and the memory is provided with a relief- comparison circuit and a relieving address storage circuit corresponding to the second address signal, and a redundant circuit corresponding to the relief- comparison circuit.
Inventors:
Toshinori Harada
Application Number:
JP2001015038A
Publication Date:
July 25, 2007
Filing Date:
January 23, 2001
Export Citation:
Assignee:
Renesas Technology Corp.
Hitachi Super LSI Systems Co., Ltd.
Hitachi Super LSI Systems Co., Ltd.
International Classes:
G11C16/06; G11C29/04; G11C11/56; G11C16/02; (IPC1-7): G11C29/00; G11C16/06; G11C16/02
Domestic Patent References:
| JP11317086A | ||||
| JP11025682A |
Attorney, Agent or Firm:
Mitsumasa Tokuwaka