To shorten a time required for writing by eliminating a useless writing period, and to simplify configuration of a writing circuit.
This device is provided with a first bias generation circuit 500 in which input digital data is held in a data register 20, this data is converted to multi-value analog quantity by a register division circuit 21 and a decoder 22, analog quantity read out from a non-volatile memory cell 60 is compared with converted analog quantity by a comparator 23, writing voltage is supplied to the memory cell 60 responding to the compared result, while two kinds of different bias voltage VBLH, VBLL are generated as this writing voltage. MOS transistors 27, 28 are inserted respectively in supply lines of bias voltage as a switch, switching writing voltage is performed by controlling selectively ON/OFF of either of the MOS transistors 27, 28 in accordance with the high-order bits D1.
UCHINO TAKASHI
NANBU SOU
