NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR CONTROLLING DATA WRITING

Title:

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR CONTROLLING DATA WRITING

Document Type and Number:

Japanese Patent JP2004071082

Kind Code:

A

Abstract:

To prevent the reliability of data protection from deteriorating and a data writing speed from lowering by controlling the distribution of the threshold voltages Vt of a memory cell after data writing for each of respective chips.

A word line voltage control circuit 12a which is a voltage control means for controlling the control voltages to be impressed to respective word lines connected with control gates has a gate voltage memory circuit 22 which is a memory means for storing the values (voltage values) determined to confine the distribution of the threshold voltages into a prescribed range according to the distribution of the threshold voltages of a plurality of the memory cells obtained by a data writing test for each chip and a word line regulator circuit 23 which is a voltage output means for outputting the prescribed control voltages to be impressed to the control gates by using the values (voltage values) stored in the circuit 22 to respective column lines.

Inventors:

HIRANO YASUAKI
KAWACHI SHUICHIRO

Application Number:

JP2002230891A

Publication Date:

March 04, 2004

Filing Date:

August 08, 2002

Export Citation:

Click for automatic bibliography generation Help

Assignee:

SHARP KK

International Classes:

H01L21/66; G11C11/56; G11C16/02; G11C16/06; G11C16/30; G11C29/00; (IPC1-7): G11C16/02; G11C16/06; H01L21/66

Attorney, Agent or Firm:

Hidesaku Yamamoto
Takaaki Yasumura
Takeshi Oshio

Previous Patent: OPTICAL PICKUP AND DISK DRIVING DEVICE

Next Patent: SEMICONDUCTOR INTEGRATED CIRCUIT